LCS-1M - A Low-Cost Hobby Oscilloscope
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Sample Logic
There are quite a few simple oscilloscope designs out there
that try to implement the full sample logic in software on the
microcontroller. Unfortunately typical inexpensive and
simple-to-use 8-bit microcontrollers lack sufficient speed, so
achievable sample rates are low. That's why I decided to use
external digital logic instead. In the current design the limit for
the sample rate (1 MS/sec) is given by the analog-to-digital
converter that I used (MAX153) rather than by the sample logic
- it would be easy to have it run to 10 MS/sec and beyond.
that try to implement the full sample logic in software on the
microcontroller. Unfortunately typical inexpensive and
simple-to-use 8-bit microcontrollers lack sufficient speed, so
achievable sample rates are low. That's why I decided to use
external digital logic instead. In the current design the limit for
the sample rate (1 MS/sec) is given by the analog-to-digital
converter that I used (MAX153) rather than by the sample logic
- it would be easy to have it run to 10 MS/sec and beyond.
| Click on the image for a larger view |
Originally I designed the scope using a Xilinx CPLD (programmable logic device), but in the end
decided to employ standard CMOS logic chips (74HCxx series) instead - a CPLD again needs special
programming hardware and software and I figured that would probably put off everybody except a few
experts. It also knocked a little bit off the component cost. This forced me to really reduce the logic
content to an absolute minimum, so thats why there is e.g. no pre-trigger option (i.e. a possibility to
capture the signal before the trigger). Maybe I'll make such a scope in the future.
The microcontroller supplies a clock signal (produced in the background through its PWM output)
which is gated (blocked) until a trigger impulse arrives through flip-flop DFF1. The XOR in front of
DFF1 acts as a programmable inverter to select triggering on either rising or falling edge. In front of it
is a Schmitt-trigger logic gate that adds some hysteresis to minimize the chance of false triggering
due to noise.
The clock signal drives a 8-bit binary counter (CTR1) which increments the address for the data
storage in the SRAM (see next page). When the counter wraps around (i.e. after reaching its
maximum, and the most significant bit goes again from 1 to 0) this triggers another flip-flop (the
second half of DFF1) which in turn gates off the clock signal. The other output (Q) of the flip-flop
produces the "DONE" signal which indicates to the microcontroller that the data acquisition has ended
and the data can now be read from the sample memory and transferred to the PC.
For this readout, the microcontroller re-enables the clock path and alternatively pulses the clock signal
and reads out one bye of sample data, which it transfers to the PC through the serial connection.
decided to employ standard CMOS logic chips (74HCxx series) instead - a CPLD again needs special
programming hardware and software and I figured that would probably put off everybody except a few
experts. It also knocked a little bit off the component cost. This forced me to really reduce the logic
content to an absolute minimum, so thats why there is e.g. no pre-trigger option (i.e. a possibility to
capture the signal before the trigger). Maybe I'll make such a scope in the future.
The microcontroller supplies a clock signal (produced in the background through its PWM output)
which is gated (blocked) until a trigger impulse arrives through flip-flop DFF1. The XOR in front of
DFF1 acts as a programmable inverter to select triggering on either rising or falling edge. In front of it
is a Schmitt-trigger logic gate that adds some hysteresis to minimize the chance of false triggering
due to noise.
The clock signal drives a 8-bit binary counter (CTR1) which increments the address for the data
storage in the SRAM (see next page). When the counter wraps around (i.e. after reaching its
maximum, and the most significant bit goes again from 1 to 0) this triggers another flip-flop (the
second half of DFF1) which in turn gates off the clock signal. The other output (Q) of the flip-flop
produces the "DONE" signal which indicates to the microcontroller that the data acquisition has ended
and the data can now be read from the sample memory and transferred to the PC.
For this readout, the microcontroller re-enables the clock path and alternatively pulses the clock signal
and reads out one bye of sample data, which it transfers to the PC through the serial connection.
