LCS-1M - A Low-Cost Hobby Oscilloscope
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Analog-to-Digital Converter; Memory
The analog-to-digital converter (ADC) is a central part of the
oscilloscope; it samples the analog signal and transforms it
into a digital number which then gets stored on the sample
memory. For this design I chose the Maxim MAX153 ADC,
which is a half-flash ADC capable to acquire up to 1 million
samples per second with a resolution on 8 bits (i.e. values of
0 to 255). This was the fastest ADC I could find that is
available in DIP package (beginner-friendly!) as a free sample.
oscilloscope; it samples the analog signal and transforms it
into a digital number which then gets stored on the sample
memory. For this design I chose the Maxim MAX153 ADC,
which is a half-flash ADC capable to acquire up to 1 million
samples per second with a resolution on 8 bits (i.e. values of
0 to 255). This was the fastest ADC I could find that is
available in DIP package (beginner-friendly!) as a free sample.
That sample rate means the scope can produce meaningful displays of signals up to about 200kHz
(in that case, there are about 5 samples per period). The ADC is driven by the same clock as the
counter, and it provides the sampled data in parallel format (8 data lines).
The sample memory is a legacy SRAM chip with a size of 2K x 8 (i.e. 2 KBytes), of which only the first
256 bytes get used. One could easily put in a larger counter (just cascade another counter IC), but I
chose to keep it down to a 8-bit address out of two reasons - first, it cuts down on components and
cost, second, a record length of 256 samples is sufficient for a very decent waveform display while at
the same time the screen update rate is relatively fluent (I measured close to 6 frames/sec with a
single channel turned on). Doubling the record length would cut the update rate roughly in half.
The acquisition circuit (ADC + SRAM) is doubled, i.e. one set for each of the scope's two channels.
The overall design would allow for an easy extension to more than two channels - just add more sets
of ADCs and SRAMs in parallel, as well as more I/O expanders to read back the SRAM content.
One little hitch that took me a while to debug is the following: The counter is a ripple counter, i.e. not all
output signals toggle at exactly the same time. This means that for a short while the address going to
the SRAM changes more or less randomly. If you keep the SRAM's write enable on during that time,
the data at those random address will get overwritten with the current sample. I got waveforms that
were recognizable but had sudden abrupt changes every few cycles. The solution was to hook up the
/WE input to a copy of the clock signal of appropriate phase so the write gets disabled whenever the
address from the counter changes.
(in that case, there are about 5 samples per period). The ADC is driven by the same clock as the
counter, and it provides the sampled data in parallel format (8 data lines).
The sample memory is a legacy SRAM chip with a size of 2K x 8 (i.e. 2 KBytes), of which only the first
256 bytes get used. One could easily put in a larger counter (just cascade another counter IC), but I
chose to keep it down to a 8-bit address out of two reasons - first, it cuts down on components and
cost, second, a record length of 256 samples is sufficient for a very decent waveform display while at
the same time the screen update rate is relatively fluent (I measured close to 6 frames/sec with a
single channel turned on). Doubling the record length would cut the update rate roughly in half.
The acquisition circuit (ADC + SRAM) is doubled, i.e. one set for each of the scope's two channels.
The overall design would allow for an easy extension to more than two channels - just add more sets
of ADCs and SRAMs in parallel, as well as more I/O expanders to read back the SRAM content.
One little hitch that took me a while to debug is the following: The counter is a ripple counter, i.e. not all
output signals toggle at exactly the same time. This means that for a short while the address going to
the SRAM changes more or less randomly. If you keep the SRAM's write enable on during that time,
the data at those random address will get overwritten with the current sample. I got waveforms that
were recognizable but had sudden abrupt changes every few cycles. The solution was to hook up the
/WE input to a copy of the clock signal of appropriate phase so the write gets disabled whenever the
address from the counter changes.
