High-Speed Digital Test Techniques
Analyzing, Modeling and Understanding
High Speed Interfaces
Using Time Domain Reflectometry
(1 day class)`
Summary:

    Keeping theory and mathematics to a minimum, this presentation aims to develop an intuitive understanding of high-speed transmission line behavior. This is an important topic
    for anyone concerned with design, analysis, troubleshooting, or qualification of high-speed
    interconnects like backplanes, printed circuit boards, high-speed serial links, cables,
    connectors, sockets etc.

    Using a compact time domain reflectometer (TDR) developed by the presenter we will
    perform a variety of life, real-time demonstrations (free-hand experiments) to investigate
    topics like delay and characteristic impedance, reflections, impedance mismatches,
    parasitics, lumped and distributed crosstalk, differential signaling, and others. We will
    show how to extract quantitative data for transmission lines and parasitics and use them to
    build equivalent models to be used in transmission path simulation.

    Towards the end we will compare TDR with the traditionally more common analysis based
    on network analyzers and show strengths and weaknesses in either approach.

Intended Audience:

    Test engineers, product engineers, characterization engineers, application engineers, chip, board or system designers with interest in test and characterization, printed circuit board
    designers, graduate students (EE, CS or physics), and anyone who deals with interfaces
    running at data rates beyond 100 Mbits/sec and/or clock frequencies above 100 MHz.

Click here to see the detailed class contents.