High-Speed Digital Test Techniques
High-Speed Digital Test Techniques
(3 - 4 day class)
Summary:

    Successful high speed digital test requires understanding the behavior of all components involved (device, test equipment, interface), as well as the interaction between them. The
    boundaries between digital and analog disappear. Connections have to be treated as
    transmission lines, with every little imperfection impacting system performance,
    deteriorating test accuracy, and reducing yield. Maintaining signal integrity is paramount in
    order to achieve meaningful results, and it requires good knowledge of signal path
    behavior, proper choice of termination techniques, and good design of the interface. While
    the tester itself is usually given and not easily modified, large improvements are possible
    by careful design of the interconnecting load board or probe interface. Apart from theoretical
    knowledge, methods to quantify the performance of a given design by measurements are
    necessary as well.

    This is the most extensive venture into high-speed test. It covers all the topics of the 1-day
    class but in much more detail, plus several additional ones (e.g. scope & probes, and ATE
    specific techniques), and also contains many more real-life examples. Live demonstrations
    with a TDR (time domain reflectometer) make signal path behavior very intuitive. Practical
    exercises will introduce the participants to modeling, simulating and optimizing their signal
    paths using PSpice and field solvers.

Intended Audience:

    Test engineers, product engineers, characterization engineers, application engineers, chip, board or system designers with interest in test and characterization, printed circuit board
    designers, and anyone who deals with data rates beyond 100 Mbits/sec and/or clock
    frequencies above 100 MHz.

Click here to see the detailed class contents.